CAN Error Interrupts

Macros
#define	CAN_IT_RAM_ACCESS_FAILURE   ( (uint32)1u << 14u )
#define	CAN_IT_ERROR_LOGGING_OVERFLOW   ( (uint32)1u << 16u )
#define	CAN_IT_RAM_WATCHDOG   ( (uint32)1u << 20u )
#define	CAN_IT_ARB_PROTOCOL_ERROR   ( (uint32)1u << 21u )
#define	CAN_IT_DATA_PROTOCOL_ERROR   ( (uint32)1u << 22u )
#define	CAN_IT_RESERVED_ADDRESS_ACCESS   ( (uint32)1u << 23u )

Detailed Description

Macro Definition Documentation

CAN_IT_ARB_PROTOCOL_ERROR

#define CAN_IT_ARB_PROTOCOL_ERROR   ( (uint32)1u << 21u )

Protocol error in arbitration phase detected

CAN_IT_DATA_PROTOCOL_ERROR

#define CAN_IT_DATA_PROTOCOL_ERROR   ( (uint32)1u << 22u )

Protocol error in data phase detected

CAN_IT_ERROR_LOGGING_OVERFLOW

#define CAN_IT_ERROR_LOGGING_OVERFLOW   ( (uint32)1u << 16u )

Overflow of FDCAN Error Logging Counter occurred

CAN_IT_RAM_ACCESS_FAILURE

#define CAN_IT_RAM_ACCESS_FAILURE   ( (uint32)1u << 14u )

Message RAM access failure occurred

CAN_IT_RAM_WATCHDOG

#define CAN_IT_RAM_WATCHDOG   ( (uint32)1u << 20u )

Message RAM Watchdog event due to missing READY

CAN_IT_RESERVED_ADDRESS_ACCESS

#define CAN_IT_RESERVED_ADDRESS_ACCESS   ( (uint32)1u << 23u )

Access to reserved address occurred