FDCAN Interrupts Group

Macros
#define	CAN_IT_GROUP_RX_FIFO0   0u
#define	CAN_IT_GROUP_RX_FIFO1   1u
#define	CAN_IT_GROUP_SMSG   2u
#define	CAN_IT_GROUP_TX_FIFO_ERROR   3u
#define	CAN_IT_GROUP_MISC   4u
#define	CAN_IT_GROUP_BIT_LINE_ERROR   5u
#define	CAN_IT_GROUP_PROTOCOL_ERROR   6u

Detailed Description

Macro Definition Documentation

CAN_IT_GROUP_BIT_LINE_ERROR

#define CAN_IT_GROUP_BIT_LINE_ERROR   5u

Bit and Line Error Interrupts Group: EPL: Error Passive and \ ELOL: Error Logging Overflow

CAN_IT_GROUP_MISC

#define CAN_IT_GROUP_MISC   4u

Misc. Interrupts Group: TOOL: Timeout Occurred, \ MRAFL: Message RAM Access Failure and TSWL: Timestamp Wraparound

CAN_IT_GROUP_PROTOCOL_ERROR

#define CAN_IT_GROUP_PROTOCOL_ERROR   6u

Protocol Error Group: ARAL: Access to Reserved Address Line, \ PEDL: Protocol Error in Data Phase Line, PEAL: Protocol Error in Arbitration Phase Line \ WDIL: Watchdog Interrupt Line, BOL: Bus_Off Status and \ EWL: Warning Status

CAN_IT_GROUP_RX_FIFO0

#define CAN_IT_GROUP_RX_FIFO0   0u

RX FIFO 0 Interrupts Group: RF0LL: Rx FIFO 0 Message Lost, \ RF0FL: Rx FIFO 0 is Full and RF0NL: Rx FIFO 0 Has New Message

CAN_IT_GROUP_RX_FIFO1

#define CAN_IT_GROUP_RX_FIFO1   1u

RX FIFO 1 Interrupts Group: RF0LL: Rx FIFO 1 Message Lost, \ RF0FL: Rx FIFO 1 is Full and RF0NL: Rx FIFO 1 Has New Message

CAN_IT_GROUP_SMSG

#define CAN_IT_GROUP_SMSG   2u

Status Message Interrupts Group: TCFL: Transmission Cancellation Finished, \ TCL: Transmission Completed and HPML: High Priority Message

CAN_IT_GROUP_TX_FIFO_ERROR

#define CAN_IT_GROUP_TX_FIFO_ERROR   3u

TX FIFO Error Interrupts Group: TEFLL: Tx Event FIFO Element Lost, \ TEFFL: Tx Event FIFO Full, TEFNL: Tx Event FIFO New Entry and \ TFEL: Tx FIFO Empty Interrupt Line