MCU PLLM Clock Divider possible values

Macros
#define	MCU_PLLM_OFFSET   4u
#define	MCU_PLLM_MASK   0x70u
#define	MCU_PLLM_DIV1   ( 0x00000000u << MCU_PLLM_OFFSET )
#define	MCU_PLLM_DIV2   ( 0x00000001u << MCU_PLLM_OFFSET )
#define	MCU_PLLM_DIV3   ( 0x00000002u << MCU_PLLM_OFFSET )
#define	MCU_PLLM_DIV4   ( 0x00000003u << MCU_PLLM_OFFSET )
#define	MCU_PLLM_DIV5   ( 0x00000004u << MCU_PLLM_OFFSET )
#define	MCU_PLLM_DIV6   ( 0x00000005u << MCU_PLLM_OFFSET )
#define	MCU_PLLM_DIV7   ( 0x00000006u << MCU_PLLM_OFFSET )
#define	MCU_PLLM_DIV8   ( 0x00000007u << MCU_PLLM_OFFSET )

Detailed Description

Macro Definition Documentation

MCU_PLLM_DIV1

#define MCU_PLLM_DIV1   ( 0x00000000u << MCU_PLLM_OFFSET )

PLL M divide by 1

MCU_PLLM_DIV2

#define MCU_PLLM_DIV2   ( 0x00000001u << MCU_PLLM_OFFSET )

PLL M divide by 2

MCU_PLLM_DIV3

#define MCU_PLLM_DIV3   ( 0x00000002u << MCU_PLLM_OFFSET )

PLL M divide by 3

MCU_PLLM_DIV4

#define MCU_PLLM_DIV4   ( 0x00000003u << MCU_PLLM_OFFSET )

PLL M divide by 4

MCU_PLLM_DIV5

#define MCU_PLLM_DIV5   ( 0x00000004u << MCU_PLLM_OFFSET )

PLL M divide by 5

MCU_PLLM_DIV6

#define MCU_PLLM_DIV6   ( 0x00000005u << MCU_PLLM_OFFSET )

PLL M divide by 6

MCU_PLLM_DIV7

#define MCU_PLLM_DIV7   ( 0x00000006u << MCU_PLLM_OFFSET )

PLL M divide by 7

MCU_PLLM_DIV8

#define MCU_PLLM_DIV8   ( 0x00000007u << MCU_PLLM_OFFSET )

PLL M divide by 8

MCU_PLLM_MASK

#define MCU_PLLM_MASK   0x70u

Mask for PLLM

MCU_PLLM_OFFSET

#define MCU_PLLM_OFFSET   4u

Bit where starts PLLM