MCU PLLP Clock Divider possible values

Macros
#define	MCU_PLLP_OFFSET   17u
#define	MCU_PLLP_MASK   0x003E0000u
#define	MCU_PLLP_DIV2   ( 1UL << MCU_PLLP_OFFSET )
#define	MCU_PLLP_DIV3   ( 2UL << MCU_PLLP_OFFSET )
#define	MCU_PLLP_DIV4   ( 3UL << MCU_PLLP_OFFSET )
#define	MCU_PLLP_DIV5   ( 4UL << MCU_PLLP_OFFSET )
#define	MCU_PLLP_DIV6   ( 5UL << MCU_PLLP_OFFSET )
#define	MCU_PLLP_DIV7   ( 6UL << MCU_PLLP_OFFSET )
#define	MCU_PLLP_DIV8   ( 7UL << MCU_PLLP_OFFSET )
#define	MCU_PLLP_DIV9   ( 8UL << MCU_PLLP_OFFSET )
#define	MCU_PLLP_DIV10   ( 9UL << MCU_PLLP_OFFSET )
#define	MCU_PLLP_DIV11   ( 10UL << MCU_PLLP_OFFSET )
#define	MCU_PLLP_DIV12   ( 11UL << MCU_PLLP_OFFSET )
#define	MCU_PLLP_DIV13   ( 12UL << MCU_PLLP_OFFSET )
#define	MCU_PLLP_DIV14   ( 13UL << MCU_PLLP_OFFSET )
#define	MCU_PLLP_DIV15   ( 14UL << MCU_PLLP_OFFSET )
#define	MCU_PLLP_DIV16   ( 15UL << MCU_PLLP_OFFSET )
#define	MCU_PLLP_DIV17   ( 16UL << MCU_PLLP_OFFSET )
#define	MCU_PLLP_DIV18   ( 17UL << MCU_PLLP_OFFSET )
#define	MCU_PLLP_DIV19   ( 18UL << MCU_PLLP_OFFSET )
#define	MCU_PLLP_DIV20   ( 19UL << MCU_PLLP_OFFSET )
#define	MCU_PLLP_DIV21   ( 20UL << MCU_PLLP_OFFSET )
#define	MCU_PLLP_DIV22   ( 21UL << MCU_PLLP_OFFSET )
#define	MCU_PLLP_DIV23   ( 22UL << MCU_PLLP_OFFSET )
#define	MCU_PLLP_DIV24   ( 23UL << MCU_PLLP_OFFSET )
#define	MCU_PLLP_DIV25   ( 24UL << MCU_PLLP_OFFSET )
#define	MCU_PLLP_DIV26   ( 25UL << MCU_PLLP_OFFSET )
#define	MCU_PLLP_DIV27   ( 26UL << MCU_PLLP_OFFSET )
#define	MCU_PLLP_DIV28   ( 27UL << MCU_PLLP_OFFSET )
#define	MCU_PLLP_DIV29   ( 28UL << MCU_PLLP_OFFSET )
#define	MCU_PLLP_DIV30   ( 29UL << MCU_PLLP_OFFSET )
#define	MCU_PLLP_DIV31   ( 30UL << MCU_PLLP_OFFSET )
#define	MCU_PLLP_DIV32   ( 31UL << MCU_PLLP_OFFSET )

Detailed Description

Macro Definition Documentation

MCU_PLLP_DIV10

#define MCU_PLLP_DIV10   ( 9UL << MCU_PLLP_OFFSET )

PLL P divide by 10

MCU_PLLP_DIV11

#define MCU_PLLP_DIV11   ( 10UL << MCU_PLLP_OFFSET )

PLL P divide by 11

MCU_PLLP_DIV12

#define MCU_PLLP_DIV12   ( 11UL << MCU_PLLP_OFFSET )

PLL P divide by 12

MCU_PLLP_DIV13

#define MCU_PLLP_DIV13   ( 12UL << MCU_PLLP_OFFSET )

PLL P divide by 13

MCU_PLLP_DIV14

#define MCU_PLLP_DIV14   ( 13UL << MCU_PLLP_OFFSET )

PLL P divide by 14

MCU_PLLP_DIV15

#define MCU_PLLP_DIV15   ( 14UL << MCU_PLLP_OFFSET )

PLL P divide by 15

MCU_PLLP_DIV16

#define MCU_PLLP_DIV16   ( 15UL << MCU_PLLP_OFFSET )

PLL P divide by 16

MCU_PLLP_DIV17

#define MCU_PLLP_DIV17   ( 16UL << MCU_PLLP_OFFSET )

PLL P divide by 17

MCU_PLLP_DIV18

#define MCU_PLLP_DIV18   ( 17UL << MCU_PLLP_OFFSET )

PLL P divide by 18

MCU_PLLP_DIV19

#define MCU_PLLP_DIV19   ( 18UL << MCU_PLLP_OFFSET )

PLL P divide by 19

MCU_PLLP_DIV2

#define MCU_PLLP_DIV2   ( 1UL << MCU_PLLP_OFFSET )

PLL P divide by 2

MCU_PLLP_DIV20

#define MCU_PLLP_DIV20   ( 19UL << MCU_PLLP_OFFSET )

PLL P divide by 20

MCU_PLLP_DIV21

#define MCU_PLLP_DIV21   ( 20UL << MCU_PLLP_OFFSET )

PLL P divide by 21

MCU_PLLP_DIV22

#define MCU_PLLP_DIV22   ( 21UL << MCU_PLLP_OFFSET )

PLL P divide by 22

MCU_PLLP_DIV23

#define MCU_PLLP_DIV23   ( 22UL << MCU_PLLP_OFFSET )

PLL P divide by 23

MCU_PLLP_DIV24

#define MCU_PLLP_DIV24   ( 23UL << MCU_PLLP_OFFSET )

PLL P divide by 24

MCU_PLLP_DIV25

#define MCU_PLLP_DIV25   ( 24UL << MCU_PLLP_OFFSET )

PLL P divide by 25

MCU_PLLP_DIV26

#define MCU_PLLP_DIV26   ( 25UL << MCU_PLLP_OFFSET )

PLL P divide by 26

MCU_PLLP_DIV27

#define MCU_PLLP_DIV27   ( 26UL << MCU_PLLP_OFFSET )

PLL P divide by 27

MCU_PLLP_DIV28

#define MCU_PLLP_DIV28   ( 27UL << MCU_PLLP_OFFSET )

PLL P divide by 28

MCU_PLLP_DIV29

#define MCU_PLLP_DIV29   ( 28UL << MCU_PLLP_OFFSET )

PLL P divide by 29

MCU_PLLP_DIV3

#define MCU_PLLP_DIV3   ( 2UL << MCU_PLLP_OFFSET )

PLL P divide by 3

MCU_PLLP_DIV30

#define MCU_PLLP_DIV30   ( 29UL << MCU_PLLP_OFFSET )

PLL P divide by 30

MCU_PLLP_DIV31

#define MCU_PLLP_DIV31   ( 30UL << MCU_PLLP_OFFSET )

PLL P divide by 31

MCU_PLLP_DIV32

#define MCU_PLLP_DIV32   ( 31UL << MCU_PLLP_OFFSET )

PLL P divide by 32

MCU_PLLP_DIV4

#define MCU_PLLP_DIV4   ( 3UL << MCU_PLLP_OFFSET )

PLL P divide by 4

MCU_PLLP_DIV5

#define MCU_PLLP_DIV5   ( 4UL << MCU_PLLP_OFFSET )

PLL P divide by 5

MCU_PLLP_DIV6

#define MCU_PLLP_DIV6   ( 5UL << MCU_PLLP_OFFSET )

PLL P divide by 6

MCU_PLLP_DIV7

#define MCU_PLLP_DIV7   ( 6UL << MCU_PLLP_OFFSET )

PLL P divide by 7

MCU_PLLP_DIV8

#define MCU_PLLP_DIV8   ( 7UL << MCU_PLLP_OFFSET )

PLL P divide by 8

MCU_PLLP_DIV9

#define MCU_PLLP_DIV9   ( 8UL << MCU_PLLP_OFFSET )

PLL P divide by 9

MCU_PLLP_MASK

#define MCU_PLLP_MASK   0x003E0000u

PLLP mask

MCU_PLLP_OFFSET

#define MCU_PLLP_OFFSET   17u

Bit where starts PLLP