MCU PLLQ Clock Divider possible values

Macros
#define	MCU_PLLQ_OFFSET   25u
#define	MCU_PLLQ_MASK   0x0E000000u
#define	MCU_PLLQ_DIV2   ( 1UL << MCU_PLLQ_OFFSET )
#define	MCU_PLLQ_DIV3   ( 2UL << MCU_PLLQ_OFFSET )
#define	MCU_PLLQ_DIV4   ( 3UL << MCU_PLLQ_OFFSET )
#define	MCU_PLLQ_DIV5   ( 4UL << MCU_PLLQ_OFFSET )
#define	MCU_PLLQ_DIV6   ( 5UL << MCU_PLLQ_OFFSET )
#define	MCU_PLLQ_DIV7   ( 6UL << MCU_PLLQ_OFFSET )
#define	MCU_PLLQ_DIV8   ( 7UL << MCU_PLLQ_OFFSET )

Detailed Description

Macro Definition Documentation

MCU_PLLQ_DIV2

#define MCU_PLLQ_DIV2   ( 1UL << MCU_PLLQ_OFFSET )

PLL Q divide by 2

MCU_PLLQ_DIV3

#define MCU_PLLQ_DIV3   ( 2UL << MCU_PLLQ_OFFSET )

PLL Q divide by 3

MCU_PLLQ_DIV4

#define MCU_PLLQ_DIV4   ( 3UL << MCU_PLLQ_OFFSET )

PLL Q divide by 4

MCU_PLLQ_DIV5

#define MCU_PLLQ_DIV5   ( 4UL << MCU_PLLQ_OFFSET )

PLL Q divide by 5

MCU_PLLQ_DIV6

#define MCU_PLLQ_DIV6   ( 5UL << MCU_PLLQ_OFFSET )

PLL Q divide by 6

MCU_PLLQ_DIV7

#define MCU_PLLQ_DIV7   ( 6UL << MCU_PLLQ_OFFSET )

PLL Q divide by 7

MCU_PLLQ_DIV8

#define MCU_PLLQ_DIV8   ( 7UL << MCU_PLLQ_OFFSET )

PLL Q divide by 8

MCU_PLLQ_MASK

#define MCU_PLLQ_MASK   0x0E000000u

PLLQ mask

MCU_PLLQ_OFFSET

#define MCU_PLLQ_OFFSET   25u

Bit where starts PLLQ