MCU PLLR Clock Divider possible values

Macros
#define	MCU_PLLR_OFFSET   9u
#define	MCU_PLLR_MASK   0xE0000000u
#define	MCU_PLLR_DIV2   ( 1UL << MCU_PLLR_OFFSET )
#define	MCU_PLLR_DIV3   ( 2UL << MCU_PLLR_OFFSET )
#define	MCU_PLLR_DIV4   ( 3UL << MCU_PLLR_OFFSET )
#define	MCU_PLLR_DIV5   ( 4UL << MCU_PLLR_OFFSET )
#define	MCU_PLLR_DIV6   ( 5UL << MCU_PLLR_OFFSET )
#define	MCU_PLLR_DIV7   ( 6UL << MCU_PLLR_OFFSET )
#define	MCU_PLLR_DIV8   ( 7UL << MCU_PLLR_OFFSET )

Detailed Description

Macro Definition Documentation

MCU_PLLR_DIV2

#define MCU_PLLR_DIV2   ( 1UL << MCU_PLLR_OFFSET )

PLL R divide by 2

MCU_PLLR_DIV3

#define MCU_PLLR_DIV3   ( 2UL << MCU_PLLR_OFFSET )

PLL R divide by 3

MCU_PLLR_DIV4

#define MCU_PLLR_DIV4   ( 3UL << MCU_PLLR_OFFSET )

PLL R divide by 4

MCU_PLLR_DIV5

#define MCU_PLLR_DIV5   ( 4UL << MCU_PLLR_OFFSET )

PLL R divide by 5

MCU_PLLR_DIV6

#define MCU_PLLR_DIV6   ( 5UL << MCU_PLLR_OFFSET )

PLL R divide by 6

MCU_PLLR_DIV7

#define MCU_PLLR_DIV7   ( 6UL << MCU_PLLR_OFFSET )

PLL R divide by 7

MCU_PLLR_DIV8

#define MCU_PLLR_DIV8   ( 7UL << MCU_PLLR_OFFSET )

PLL R divide by 8

MCU_PLLR_MASK

#define MCU_PLLR_MASK   0xE0000000u

PLLR mask

MCU_PLLR_OFFSET

#define MCU_PLLR_OFFSET   9u

Bit where starts PLLR