CAN Controller Area Network. More...

#include <Registers.h>

Data Fields
volatile uint32	CREL

volatile uint32	ENDN

uint32	RESERVED1

volatile uint32	DBTP

volatile uint32	TEST

volatile uint32	RWD

volatile uint32	CCCR

volatile uint32	NBTP

volatile uint32	TSCC

volatile uint32	TSCV

volatile uint32	TOCC

volatile uint32	TOCV

uint32	RESERVED2 [4]

volatile uint32	ECR

volatile uint32	PSR

volatile uint32	TDCR

uint32	RESERVED3

volatile uint32	IR

volatile uint32	IE

volatile uint32	ILS

volatile uint32	ILE

uint32	RESERVED4 [8]

volatile uint32	RXGFC

volatile uint32	XIDAM

volatile uint32	HPMS

uint32	RESERVED5

volatile uint32	RXF0S

volatile uint32	RXF0A

volatile uint32	RXF1S

volatile uint32	RXF1A

uint32	RESERVED6 [8]

volatile uint32	TXBC

volatile uint32	TXFQS

volatile uint32	TXBRP

volatile uint32	TXBAR

volatile uint32	TXBCR

volatile uint32	TXBTO

volatile uint32	TXBCF

volatile uint32	TXBTIE

volatile uint32	TXBCIE

volatile uint32	TXEFS

volatile uint32	TXEFA

uint32	RESERVED7 [5]

volatile uint32	CKDIV

Detailed Description

CAN Controller Area Network.

Field Documentation

◆ CCCR

volatile uint32 Can_RegisterType::CCCR

FDCAN CC Control register, Address offset: 0x018

◆ CKDIV

volatile uint32 Can_RegisterType::CKDIV

FDCAN clock divider register, Address offset: 0x100

◆ CREL

volatile uint32 Can_RegisterType::CREL

FDCAN Core Release register, Address offset: 0x000

◆ DBTP

volatile uint32 Can_RegisterType::DBTP

FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C

◆ ECR

volatile uint32 Can_RegisterType::ECR

FDCAN Error Counter register, Address offset: 0x040

◆ ENDN

volatile uint32 Can_RegisterType::ENDN

FDCAN Endian register, Address offset: 0x004

◆ HPMS

volatile uint32 Can_RegisterType::HPMS

FDCAN High Priority Message Status register, Address offset: 0x088

◆ IE

volatile uint32 Can_RegisterType::IE

FDCAN Interrupt Enable register, Address offset: 0x054

◆ ILE

volatile uint32 Can_RegisterType::ILE

FDCAN Interrupt Line Enable register, Address offset: 0x05C

◆ ILS

volatile uint32 Can_RegisterType::ILS

FDCAN Interrupt Line Select register, Address offset: 0x058

◆ IR

volatile uint32 Can_RegisterType::IR

FDCAN Interrupt register, Address offset: 0x050

◆ NBTP

volatile uint32 Can_RegisterType::NBTP

FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C

◆ PSR

volatile uint32 Can_RegisterType::PSR

FDCAN Protocol Status register, Address offset: 0x044

◆ RESERVED1

uint32 Can_RegisterType::RESERVED1

Reserved, 0x008

◆ RESERVED2

uint32 Can_RegisterType::RESERVED2[4]

Reserved, 0x030 - 0x03C

◆ RESERVED3

uint32 Can_RegisterType::RESERVED3

Reserved, 0x04C

◆ RESERVED4

uint32 Can_RegisterType::RESERVED4[8]

Reserved, 0x060 - 0x07C

◆ RESERVED5

uint32 Can_RegisterType::RESERVED5

Reserved, 0x08C

◆ RESERVED6

uint32 Can_RegisterType::RESERVED6[8]

Reserved, 0x0A0 - 0x0BC

◆ RESERVED7

uint32 Can_RegisterType::RESERVED7[5]

Reserved, 0x0EC - 0x0FC

◆ RWD

volatile uint32 Can_RegisterType::RWD

FDCAN RAM Watchdog register, Address offset: 0x014

◆ RXF0A

volatile uint32 Can_RegisterType::RXF0A

FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094

◆ RXF0S

volatile uint32 Can_RegisterType::RXF0S

FDCAN Rx FIFO 0 Status register, Address offset: 0x090

◆ RXF1A

volatile uint32 Can_RegisterType::RXF1A

FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C

◆ RXF1S

volatile uint32 Can_RegisterType::RXF1S

FDCAN Rx FIFO 1 Status register, Address offset: 0x098

◆ RXGFC

volatile uint32 Can_RegisterType::RXGFC

FDCAN Global Filter Configuration register, Address offset: 0x080

◆ TDCR

volatile uint32 Can_RegisterType::TDCR

FDCAN Transmitter Delay Compensation register, Address offset: 0x048

◆ TEST

volatile uint32 Can_RegisterType::TEST

FDCAN Test register, Address offset: 0x010

◆ TOCC

volatile uint32 Can_RegisterType::TOCC

FDCAN Timeout Counter Configuration register, Address offset: 0x028

◆ TOCV

volatile uint32 Can_RegisterType::TOCV

FDCAN Timeout Counter Value register, Address offset: 0x02C

◆ TSCC

volatile uint32 Can_RegisterType::TSCC

FDCAN Timestamp Counter Configuration register, Address offset: 0x020

◆ TSCV

volatile uint32 Can_RegisterType::TSCV

FDCAN Timestamp Counter Value register, Address offset: 0x024

◆ TXBAR

volatile uint32 Can_RegisterType::TXBAR

FDCAN Tx Buffer Add Request register, Address offset: 0x0CC

◆ TXBC

volatile uint32 Can_RegisterType::TXBC

FDCAN Tx Buffer Configuration register, Address offset: 0x0C0

◆ TXBCF

volatile uint32 Can_RegisterType::TXBCF

FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8

◆ TXBCIE

volatile uint32 Can_RegisterType::TXBCIE

FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0

◆ TXBCR

volatile uint32 Can_RegisterType::TXBCR

FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0

◆ TXBRP

volatile uint32 Can_RegisterType::TXBRP

FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8

◆ TXBTIE

volatile uint32 Can_RegisterType::TXBTIE

FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC

◆ TXBTO

volatile uint32 Can_RegisterType::TXBTO

FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4

◆ TXEFA

volatile uint32 Can_RegisterType::TXEFA

FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8

◆ TXEFS

volatile uint32 Can_RegisterType::TXEFS

FDCAN Tx Event FIFO Status register, Address offset: 0x0E4

◆ TXFQS

volatile uint32 Can_RegisterType::TXFQS

FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4

◆ XIDAM

volatile uint32 Can_RegisterType::XIDAM

FDCAN Extended ID AND Mask register, Address offset: 0x084

The documentation for this struct was generated from the following file:

autosar/mcal/regs/Registers.h

Data Fields