Registers.h

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#ifndef REGISTERS_H
#define REGISTERS_H

typedef enum
{
    /******  Cortex-M0+ Processor Exceptions Numbers ***************************************************************/
    NonMaskableInt_IRQn = -14,                   
    HardFault_IRQn      = -13,                   
    SVCall_IRQn         = -5,                    
    PendSV_IRQn         = -2,                    
    SysTick_IRQn        = -1,                    
                                                 /******  STM32G0xxxx specific Interrupt Numbers ************************/
    WWDG_IRQn                              = 0,  
    PVD_VDDIO2_IRQn                        = 1,  
    RTC_TAMP_IRQn                          = 2,  
    FLASH_IRQn                             = 3,  
    RCC_CRS_IRQn                           = 4,  
    EXTI0_1_IRQn                           = 5,  
    EXTI2_3_IRQn                           = 6,  
    EXTI4_15_IRQn                          = 7,  
    USB_UCPD1_2_IRQn                       = 8,  
    DMA1_Channel1_IRQn                     = 9,  
    DMA1_Channel2_3_IRQn                   = 10, 
    DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQn = 11, 
    ADC1_COMP_IRQn                         = 12, 
    TIM1_BRK_UP_TRG_COM_IRQn               = 13, 
    TIM1_CC_IRQn                           = 14, 
    TIM2_IRQn                              = 15, 
    TIM3_TIM4_IRQn                         = 16, 
    TIM6_DAC_LPTIM1_IRQn                   = 17, 
    TIM7_LPTIM2_IRQn                       = 18, 
    TIM14_IRQn                             = 19, 
    TIM15_IRQn                             = 20, 
    TIM16_FDCAN_IT0_IRQn                   = 21, 
    TIM17_FDCAN_IT1_IRQn                   = 22, 
    I2C1_IRQn                              = 23, 
    I2C2_3_IRQn                            = 24, 
    SPI1_IRQn                              = 25, 
    SPI2_3_IRQn                            = 26, 
    USART1_IRQn                            = 27, 
    USART2_LPUART2_IRQn                    = 28, 
    USART3_4_5_6_LPUART1_IRQn              = 29, 
    CEC_IRQn                               = 30, 
} Nvic_IrqType;

#define FLASH_BASE     ( 0x08000000UL )               
#define SRAM_BASE      ( 0x20000000UL )               
#define PERIPH_BASE    ( 0x40000000UL )               
#define IOPORT_BASE    ( 0x50000000UL )               
#define SCS_BASE       ( 0xE000E000UL )               
#define APBPERIPH_BASE ( PERIPH_BASE )                
#define AHBPERIPH_BASE ( PERIPH_BASE + 0x00020000UL ) 

typedef struct
{
    volatile uint32 ISER[ 1U ];       
    volatile uint32 RESERVED0[ 31U ]; 
    volatile uint32 ICER[ 1U ];       
    volatile uint32 RESERVED1[ 31U ]; 
    volatile uint32 ISPR[ 1U ];       
    volatile uint32 RESERVED2[ 31U ]; 
    volatile uint32 ICPR[ 1U ];       
    volatile uint32 RESERVED3[ 31U ]; 
    volatile uint32 RESERVED4[ 64U ]; 
    volatile uint32 IP[ 8U ];         
} Nvic_RegisterType;

#define NVIC_BASE ( SCS_BASE + 0x0100UL )            
#define NVIC      ( (Nvic_RegisterType *)NVIC_BASE ) 

typedef struct
{
    volatile uint32 CR;        
    volatile uint32 ICSCR;     
    volatile uint32 CFGR;      
    volatile uint32 PLLCFGR;   
    volatile uint32 Reserv;    
    volatile uint32 CRRCR;     
    volatile uint32 CIER;      
    volatile uint32 CIFR;      
    volatile uint32 CICR;      
    volatile uint32 IOPRSTR;   
    volatile uint32 AHBRSTR;   
    volatile uint32 APBRSTR1;  
    volatile uint32 APBRSTR2;  
    volatile uint32 IOPENR;    
    volatile uint32 AHBENR;    
    volatile uint32 APBENR1;   
    volatile uint32 APBENR2;   
    volatile uint32 IOPSMENR;  
    volatile uint32 AHBSMENR;  
    volatile uint32 APBSMENR1; 
    volatile uint32 APBSMENR2; 
    volatile uint32 CCIPR;     
    volatile uint32 CCIPR2;    
    volatile uint32 BDCR;      
    volatile uint32 CSR;       
} Rcc_RegisterType;

#define RCC_BASE ( AHBPERIPH_BASE + 0x00001000UL ) 
#define RCC      ( (Rcc_RegisterType *)RCC_BASE )  

typedef struct
{
    volatile uint32 MODER;   
    volatile uint32 OTYPER;  
    volatile uint32 OSPEEDR; 
    volatile uint32 PUPDR;   
    volatile uint32 IDR;     
    volatile uint32 ODR;     
    volatile uint32 BSRR;    
    volatile uint32 LCKR;    
    volatile uint32 AFRL;    
    volatile uint32 AFRH;    
    volatile uint32 BRR;     
} Port_RegisterType;

#define PORTA_BASE ( IOPORT_BASE + 0x00000000UL )      
#define PORTB_BASE ( IOPORT_BASE + 0x00000400UL )      
#define PORTC_BASE ( IOPORT_BASE + 0x00000800UL )      
#define PORTD_BASE ( IOPORT_BASE + 0x00000C00UL )      
#define PORTE_BASE ( IOPORT_BASE + 0x00001000UL )      
#define PORTF_BASE ( IOPORT_BASE + 0x00001400UL )      
#define PORTA      ( (Port_RegisterType *)PORTA_BASE ) 
#define PORTB      ( (Port_RegisterType *)PORTB_BASE ) 
#define PORTC      ( (Port_RegisterType *)PORTC_BASE ) 
#define PORTD      ( (Port_RegisterType *)PORTD_BASE ) 
#define PORTE      ( (Port_RegisterType *)PORTE_BASE ) 
#define PORTF      ( (Port_RegisterType *)PORTF_BASE ) 

typedef struct
{
    volatile uint32 Reserved1[ 4 ]; 
    volatile uint32 IDR;            
    volatile uint32 ODR;            
    volatile uint32 BSRR;           
    volatile uint32 Reserved2[ 3 ]; 
    volatile uint32 BRR;            
} Dio_RegisterType;

#define DIOA                 ( (Dio_RegisterType *)PORTA_BASE ) 
#define DIOB                 ( (Dio_RegisterType *)PORTB_BASE ) 
#define DIOC                 ( (Dio_RegisterType *)PORTC_BASE ) 
#define DIOD                 ( (Dio_RegisterType *)PORTD_BASE ) 
#define DIOE                 ( (Dio_RegisterType *)PORTE_BASE ) 
#define DIOF                 ( (Dio_RegisterType *)PORTF_BASE ) 

#define RCC_GPIOA_CLK_EN( )  RCC->IOPENR |= 0x01u; 
#define RCC_GPIOB_CLK_EN( )  RCC->IOPENR |= 0x02u; 
#define RCC_GPIOC_CLK_EN( )  RCC->IOPENR |= 0x04u; 
#define RCC_GPIOD_CLK_EN( )  RCC->IOPENR |= 0x08u; 
#define RCC_GPIOE_CLK_EN( )  RCC->IOPENR |= 0x10u; 
#define RCC_GPIOF_CLK_EN( )  RCC->IOPENR |= 0x20u; 

#define RCC_GPIOA_CLK_DIS( ) RCC->IOPENR &= ~( 1u << 0u ); 
#define RCC_GPIOB_CLK_DIS( ) RCC->IOPENR &= ~( 1u << 1u ); 
#define RCC_GPIOC_CLK_DIS( ) RCC->IOPENR &= ~( 1u << 2u ); 
#define RCC_GPIOD_CLK_DIS( ) RCC->IOPENR &= ~( 1u << 3u ); 
#define RCC_GPIOE_CLK_DIS( ) RCC->IOPENR &= ~( 1u << 4u ); 
#define RCC_GPIOF_CLK_DIS( ) RCC->IOPENR &= ~( 1u << 5u ); 

typedef struct
{
    volatile uint32 CR1;             
    volatile uint32 CR2;             
    volatile uint32 Reserved0;       
    volatile uint32 DIER;            
    volatile uint32 SR;              
    volatile uint32 EGR;             
    volatile uint32 Reserved1[ 3u ]; 
    volatile uint32 CNT;             
    volatile uint32 PSC;             
    volatile uint32 ARR;             
} Gpt_RegisterType;

#define TIM6_BASE ( PERIPH_BASE + 0x00001000UL )    
#define TIM7_BASE ( PERIPH_BASE + 0x00001400UL )    
#define TIM6      ( (Gpt_RegisterType *)TIM6_BASE ) 
#define TIM7      ( (Gpt_RegisterType *)TIM7_BASE ) 

typedef struct
{
    volatile uint32 CREL;   
    volatile uint32 ENDN;   
    uint32 RESERVED1;       
    volatile uint32 DBTP;   
    volatile uint32 TEST;   
    volatile uint32 RWD;    
    volatile uint32 CCCR;   
    volatile uint32 NBTP;   
    volatile uint32 TSCC;   
    volatile uint32 TSCV;   
    volatile uint32 TOCC;   
    volatile uint32 TOCV;   
    uint32 RESERVED2[ 4 ];  
    volatile uint32 ECR;    
    volatile uint32 PSR;    
    volatile uint32 TDCR;   
    uint32 RESERVED3;       
    volatile uint32 IR;     
    volatile uint32 IE;     
    volatile uint32 ILS;    
    volatile uint32 ILE;    
    uint32 RESERVED4[ 8 ];  
    volatile uint32 RXGFC;  
    volatile uint32 XIDAM;  
    volatile uint32 HPMS;   
    uint32 RESERVED5;       
    volatile uint32 RXF0S;  
    volatile uint32 RXF0A;  
    volatile uint32 RXF1S;  
    volatile uint32 RXF1A;  
    uint32 RESERVED6[ 8 ];  
    volatile uint32 TXBC;   
    volatile uint32 TXFQS;  
    volatile uint32 TXBRP;  
    volatile uint32 TXBAR;  
    volatile uint32 TXBCR;  
    volatile uint32 TXBTO;  
    volatile uint32 TXBCF;  
    volatile uint32 TXBTIE; 
    volatile uint32 TXBCIE; 
    volatile uint32 TXEFS;  
    volatile uint32 TXEFA;  
    uint32 RESERVED7[ 5 ];  
    volatile uint32 CKDIV;  
} Can_RegisterType;

#define CAN1_BASE ( PERIPH_BASE + 0x00006400UL )    
#define CAN2_BASE ( PERIPH_BASE + 0x00006800UL )    
#define CAN1      ( (Can_RegisterType *)CAN1_BASE ) 
#define CAN2      ( (Can_RegisterType *)CAN2_BASE ) 

typedef struct
{
    volatile uint32 FLSSA[ 28 ]; 
    volatile uint32 FLESA[ 16 ]; 
    volatile uint32 F0SA[ 54 ];  
    volatile uint32 F1SA[ 54 ];  
    volatile uint32 EFSA[ 6 ];   
    volatile uint32 TBSA[ 54 ];  
} SramCan_RegisterType;

#define SRAMCAN1_BASE ( APBPERIPH_BASE + 0x0000B400UL )         
#define SRAMCAN2_BASE ( APBPERIPH_BASE + 0x0000B800UL )         
#define SRAMCAN1      ( (SramCan_RegisterType *)SRAMCAN1_BASE ) 
#define SRAMCAN2      ( (SramCan_RegisterType *)SRAMCAN2_BASE ) 
 
#endif