STM32G0 MCAL 0.0.1
Tiny MCAL for educational purpose.
Loading...
Searching...
No Matches
Data Fields
Rcc_RegisterType Struct Reference

RCC registers struct. More...

#include <Registers.h>

Data Fields

volatile uint32 CR
 
volatile uint32 ICSCR
 
volatile uint32 CFGR
 
volatile uint32 PLLCFGR
 
volatile uint32 Reserv
 
volatile uint32 CRRCR
 
volatile uint32 CIER
 
volatile uint32 CIFR
 
volatile uint32 CICR
 
volatile uint32 IOPRSTR
 
volatile uint32 AHBRSTR
 
volatile uint32 APBRSTR1
 
volatile uint32 APBRSTR2
 
volatile uint32 IOPENR
 
volatile uint32 AHBENR
 
volatile uint32 APBENR1
 
volatile uint32 APBENR2
 
volatile uint32 IOPSMENR
 
volatile uint32 AHBSMENR
 
volatile uint32 APBSMENR1
 
volatile uint32 APBSMENR2
 
volatile uint32 CCIPR
 
volatile uint32 CCIPR2
 
volatile uint32 BDCR
 
volatile uint32 CSR
 

Detailed Description

RCC registers struct.

Field Documentation

◆ AHBENR

volatile uint32 Rcc_RegisterType::AHBENR

AHB peripheral clock enable register

◆ AHBRSTR

volatile uint32 Rcc_RegisterType::AHBRSTR

AHB peripheral reset register

◆ AHBSMENR

volatile uint32 Rcc_RegisterType::AHBSMENR

AHB peripheral clock enable in sleep/stop mode register

◆ APBENR1

volatile uint32 Rcc_RegisterType::APBENR1

APB1 peripheral clock enable register

◆ APBENR2

volatile uint32 Rcc_RegisterType::APBENR2

APB2 peripheral clock enable register

◆ APBRSTR1

volatile uint32 Rcc_RegisterType::APBRSTR1

APB1 peripheral reset register

◆ APBRSTR2

volatile uint32 Rcc_RegisterType::APBRSTR2

APB2 peripheral reset register

◆ APBSMENR1

volatile uint32 Rcc_RegisterType::APBSMENR1

APB1 peripheral clock enable in Sleep/stop mode register

◆ APBSMENR2

volatile uint32 Rcc_RegisterType::APBSMENR2

APB2 peripheral clock enable in Sleep/stop mode register

◆ BDCR

volatile uint32 Rcc_RegisterType::BDCR

RTC domain control register

◆ CCIPR

volatile uint32 Rcc_RegisterType::CCIPR

Peripherals independent clock configuration register

◆ CCIPR2

volatile uint32 Rcc_RegisterType::CCIPR2

Peripherals independent clock configuration register 2

◆ CFGR

volatile uint32 Rcc_RegisterType::CFGR

Clock configuration register

◆ CICR

volatile uint32 Rcc_RegisterType::CICR

Clock interrupt clear register

◆ CIER

volatile uint32 Rcc_RegisterType::CIER

Clock interrupt enable register

◆ CIFR

volatile uint32 Rcc_RegisterType::CIFR

Clock interrupt flag register

◆ CR

volatile uint32 Rcc_RegisterType::CR

RCC clock control register

◆ CRRCR

volatile uint32 Rcc_RegisterType::CRRCR

clock recovery RC register

◆ CSR

volatile uint32 Rcc_RegisterType::CSR

control/status register

◆ ICSCR

volatile uint32 Rcc_RegisterType::ICSCR

RCC internal clock sources calibration register

◆ IOPENR

volatile uint32 Rcc_RegisterType::IOPENR

I/O port clock enable register

◆ IOPRSTR

volatile uint32 Rcc_RegisterType::IOPRSTR

I/O port reset register

◆ IOPSMENR

volatile uint32 Rcc_RegisterType::IOPSMENR

I/O port in Sleep mode clock enable register

◆ PLLCFGR

volatile uint32 Rcc_RegisterType::PLLCFGR

PLL configuration register

◆ Reserv

volatile uint32 Rcc_RegisterType::Reserv

Reserv memory space

The documentation for this struct was generated from the following file: