Registers.h File Reference

This file contains definitions and configurations for the NVIC. More...

Go to the source code of this file.

Data Structures
struct	Nvic_RegisterType
	Nested Vectored Interrupt Controller (NVIC) structure. More...
struct	Rcc_RegisterType
	RCC registers struct. More...
struct	Port_RegisterType
	GPIOS registers struct. More...
struct	Dio_RegisterType
	GPIOS registers struct for Dio. More...
struct	Gpt_RegisterType
	GPT registers struct. More...
struct	Can_RegisterType
	CAN Controller Area Network. More...
struct	SramCan_RegisterType
	SRAM CAN for Hardware objects. More...

Macros
#define	FLASH_BASE   ( 0x08000000UL )
#define	SRAM_BASE   ( 0x20000000UL )
#define	PERIPH_BASE   ( 0x40000000UL )
#define	IOPORT_BASE   ( 0x50000000UL )
#define	SCS_BASE   ( 0xE000E000UL )
#define	APBPERIPH_BASE   ( PERIPH_BASE )
#define	AHBPERIPH_BASE   ( PERIPH_BASE + 0x00020000UL )
#define	NVIC_BASE   ( SCS_BASE + 0x0100UL )
#define	NVIC   ( (Nvic_RegisterType *)NVIC_BASE )
#define	RCC_BASE   ( AHBPERIPH_BASE + 0x00001000UL )
#define	RCC   ( (Rcc_RegisterType *)RCC_BASE )
#define	PORTA_BASE   ( IOPORT_BASE + 0x00000000UL )
#define	PORTB_BASE   ( IOPORT_BASE + 0x00000400UL )
#define	PORTC_BASE   ( IOPORT_BASE + 0x00000800UL )
#define	PORTD_BASE   ( IOPORT_BASE + 0x00000C00UL )
#define	PORTE_BASE   ( IOPORT_BASE + 0x00001000UL )
#define	PORTF_BASE   ( IOPORT_BASE + 0x00001400UL )
#define	PORTA   ( (Port_RegisterType *)PORTA_BASE )
#define	PORTB   ( (Port_RegisterType *)PORTB_BASE )
#define	PORTC   ( (Port_RegisterType *)PORTC_BASE )
#define	PORTD   ( (Port_RegisterType *)PORTD_BASE )
#define	PORTE   ( (Port_RegisterType *)PORTE_BASE )
#define	PORTF   ( (Port_RegisterType *)PORTF_BASE )
#define	DIOA   ( (Dio_RegisterType *)PORTA_BASE )
#define	DIOB   ( (Dio_RegisterType *)PORTB_BASE )
#define	DIOC   ( (Dio_RegisterType *)PORTC_BASE )
#define	DIOD   ( (Dio_RegisterType *)PORTD_BASE )
#define	DIOE   ( (Dio_RegisterType *)PORTE_BASE )
#define	DIOF   ( (Dio_RegisterType *)PORTF_BASE )
#define	RCC_GPIOA_CLK_EN()
#define	RCC_GPIOB_CLK_EN()
#define	RCC_GPIOC_CLK_EN()
#define	RCC_GPIOD_CLK_EN()
#define	RCC_GPIOE_CLK_EN()
#define	RCC_GPIOF_CLK_EN()
#define	RCC_GPIOA_CLK_DIS()
#define	RCC_GPIOB_CLK_DIS()
#define	RCC_GPIOC_CLK_DIS()
#define	RCC_GPIOD_CLK_DIS()
#define	RCC_GPIOE_CLK_DIS()
#define	RCC_GPIOF_CLK_DIS()
#define	TIM6_BASE   ( PERIPH_BASE + 0x00001000UL )
#define	TIM7_BASE   ( PERIPH_BASE + 0x00001400UL )
#define	TIM6   ( (Gpt_RegisterType *)TIM6_BASE )
#define	TIM7   ( (Gpt_RegisterType *)TIM7_BASE )
#define	CAN1_BASE   ( PERIPH_BASE + 0x00006400UL )
#define	CAN2_BASE   ( PERIPH_BASE + 0x00006800UL )
#define	CAN1   ( (Can_RegisterType *)CAN1_BASE )
#define	CAN2   ( (Can_RegisterType *)CAN2_BASE )
#define	SRAMCAN1_BASE   ( APBPERIPH_BASE + 0x0000B400UL )
#define	SRAMCAN2_BASE   ( APBPERIPH_BASE + 0x0000B800UL )
#define	SRAMCAN1   ( (SramCan_RegisterType *)SRAMCAN1_BASE )
#define	SRAMCAN2   ( (SramCan_RegisterType *)SRAMCAN2_BASE )

Enumerations
enum	Nvic_IrqType {   NonMaskableInt_IRQn = -14 , HardFault_IRQn = -13 , SVCall_IRQn = -5 , PendSV_IRQn = -2 ,   SysTick_IRQn = -1 , WWDG_IRQn = 0 , PVD_VDDIO2_IRQn = 1 , RTC_TAMP_IRQn = 2 ,   FLASH_IRQn = 3 , RCC_CRS_IRQn = 4 , EXTI0_1_IRQn = 5 , EXTI2_3_IRQn = 6 ,   EXTI4_15_IRQn = 7 , USB_UCPD1_2_IRQn = 8 , DMA1_Channel1_IRQn = 9 , DMA1_Channel2_3_IRQn = 10 ,   DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQn = 11 , ADC1_COMP_IRQn = 12 , TIM1_BRK_UP_TRG_COM_IRQn = 13 , TIM1_CC_IRQn = 14 ,   TIM2_IRQn = 15 , TIM3_TIM4_IRQn = 16 , TIM6_DAC_LPTIM1_IRQn = 17 , TIM7_LPTIM2_IRQn = 18 ,   TIM14_IRQn = 19 , TIM15_IRQn = 20 , TIM16_FDCAN_IT0_IRQn = 21 , TIM17_FDCAN_IT1_IRQn = 22 ,   I2C1_IRQn = 23 , I2C2_3_IRQn = 24 , SPI1_IRQn = 25 , SPI2_3_IRQn = 26 ,   USART1_IRQn = 27 , USART2_LPUART2_IRQn = 28 , USART3_4_5_6_LPUART1_IRQn = 29 , CEC_IRQn = 30 }
	Nested Vectored Interrupt Controller (NVIC) interrupt types for Cortex-M0+ and STM32G0xxxx. This enumeration lists the Cortex-M0+ exceptions and STM32G0xxxx microcontroller interrupts. More...

Detailed Description

This file contains definitions and configurations for the NVIC.

This file defines addresses, interrupts, and NVIC structures for Cortex-M0+.

Enumeration Type Documentation

Nvic_IrqType

enum Nvic_IrqType

Nested Vectored Interrupt Controller (NVIC) interrupt types for Cortex-M0+ and STM32G0xxxx. This enumeration lists the Cortex-M0+ exceptions and STM32G0xxxx microcontroller interrupts.

Enumerator
NonMaskableInt_IRQn	2 Non Maskable Interrupt
HardFault_IRQn	3 Cortex-M Hard Fault Interrupt
SVCall_IRQn	11 Cortex-M SV Call Interrupt
PendSV_IRQn	14 Cortex-M Pend SV Interrupt
SysTick_IRQn	15 Cortex-M System Tick Interrupt
WWDG_IRQn	Window WatchDog Interrupt
PVD_VDDIO2_IRQn	PVD through EXTI line 16, PVM (monit. VDDIO2) through EXTI line 34
RTC_TAMP_IRQn	RTC interrupt through the EXTI line 19 & 21
FLASH_IRQn	FLASH global Interrupt
RCC_CRS_IRQn	RCC and CRS global Interrupt
EXTI0_1_IRQn	EXTI 0 and 1 Interrupts
EXTI2_3_IRQn	EXTI Line 2 and 3 Interrupts
EXTI4_15_IRQn	EXTI Line 4 to 15 Interrupts
USB_UCPD1_2_IRQn	USB, UCPD1 and UCPD2 global Interrupt
DMA1_Channel1_IRQn	DMA1 Channel 1 Interrupt
DMA1_Channel2_3_IRQn	DMA1 Channel 2 and Channel 3 Interrupts
DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQn	DMA1 Ch4 to Ch7, DMA2 Ch1 to Ch5 and DMAMUX1 Overrun Interrupts
ADC1_COMP_IRQn	ADC1, COMP1,COMP2, COMP3 Interrupts (combined with EXTI 17 & 18)
TIM1_BRK_UP_TRG_COM_IRQn	TIM1 Break, Update, Trigger and Commutation Interrupts
TIM1_CC_IRQn	TIM1 Capture Compare Interrupt
TIM2_IRQn	TIM2 Interrupt
TIM3_TIM4_IRQn	TIM3, TIM4 global Interrupt
TIM6_DAC_LPTIM1_IRQn	TIM6, DAC and LPTIM1 global Interrupts
TIM7_LPTIM2_IRQn	TIM7 and LPTIM2 global Interrupt
TIM14_IRQn	TIM14 global Interrupt
TIM15_IRQn	TIM15 global Interrupt
TIM16_FDCAN_IT0_IRQn	TIM16, FDCAN1_IT0 and FDCAN2_IT0 Interrupt
TIM17_FDCAN_IT1_IRQn	TIM17, FDCAN1_IT1 and FDCAN2_IT1 Interrupt
I2C1_IRQn	I2C1 Interrupt (combined with EXTI 23)
I2C2_3_IRQn	I2C2, I2C3 Interrupt (combined with EXTI 24 and EXTI 22)
SPI1_IRQn	SPI1/I2S1 Interrupt
SPI2_3_IRQn	SPI2/I2S2, SPI3/I2S3 Interrupt
USART1_IRQn	USART1 Interrupt
USART2_LPUART2_IRQn	USART2 + LPUART2 Interrupt
USART3_4_5_6_LPUART1_IRQn	USART3, USART4, USART5, USART6, LPUART1 globlal Interrupts (combined with EXTI 28)
CEC_IRQn	CEC Interrupt(combined with EXTI 27)