Mcu_Types.h

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#ifndef MCU_TYPES_H__
#define MCU_TYPES_H__
 
#include "Registers.h"
#include "Std_Types.h"

#define MCU_ID_INIT                 0x00u 
#define MCU_ID_INIT_RAM             0x01u 
#define MCU_ID_INIT_CLOCK           0x02u 
#define MCU_ID_DISTRIBUTE_PLL_CLOCK 0x03u 
#define MCU_ID_GET_PLL_STATUS       0x04u 
#define MCU_ID_GET_RESET_REASON     0x05u 
#define MCU_ID_GET_RESET_RAW_VALUE  0x06u 
#define MCU_ID_PERFORM_RESET        0x07u 
#define MCU_ID_SET_MODE             0x08u 
#define MCU_ID_GET_VERSION_INFO     0x09u 
#define MCU_ID_GET_RAM_STATE        0x0Au 

#define MCU_E_PARAM_CONFIG          0x0Au 
#define MCU_E_PARAM_CLOCK           0x0Bu 
#define MCU_E_PARAM_MODE            0x0Cu 
#define MCU_E_PARAM_RAMSECTION      0x0Du 
#define MCU_E_PLL_NOT_LOCKED        0x0Eu 
#define MCU_E_UNINIT                0x0Fu 
#define MCU_E_PARAM_POINTER         0x10u 
#define MCU_E_INIT_FAILED           0x11u 

#ifndef UTEST
#define MCU_STATIC static 
#else
#define MCU_STATIC 
#endif

#define MCU_PLL_SOURCE_MASK          0x03u       
#define MCU_PLL_SOURCE_NONE          0x00000000u 
#define MCU_PLL_SOURCE_NOT_VALID     0x00000001u 
#define MCU_PLL_SOURCE_HSI           0x00000002u 
#define MCU_PLL_SOURCE_HSE           0x00000003u 

#define MCU_PLL_OUTPUT_PLLP          0u 
#define MCU_PLL_OUTPUT_PLLQ          1u 
#define MCU_PLL_OUTPUT_PLLR          2u 

#define MCU_PLLM_OFFSET              4u                                 
#define MCU_PLLM_MASK                0x70u                              
#define MCU_PLLM_DIV1                ( 0x00000000u << MCU_PLLM_OFFSET ) 
#define MCU_PLLM_DIV2                ( 0x00000001u << MCU_PLLM_OFFSET ) 
#define MCU_PLLM_DIV3                ( 0x00000002u << MCU_PLLM_OFFSET ) 
#define MCU_PLLM_DIV4                ( 0x00000003u << MCU_PLLM_OFFSET ) 
#define MCU_PLLM_DIV5                ( 0x00000004u << MCU_PLLM_OFFSET ) 
#define MCU_PLLM_DIV6                ( 0x00000005u << MCU_PLLM_OFFSET ) 
#define MCU_PLLM_DIV7                ( 0x00000006u << MCU_PLLM_OFFSET ) 
#define MCU_PLLM_DIV8                ( 0x00000007u << MCU_PLLM_OFFSET ) 

#define MCU_PLLN_OFFSET              8u      
#define MCU_PLLN_MASK                0x7F00u 
#define MCU_PLLN_MIN_VALUE           8u      
#define MCU_PLLN_MAX_VALUE           86u     

#define MCU_PLLP_OFFSET              17u                         
#define MCU_PLLP_MASK                0x003E0000u                 
#define MCU_PLLP_DIV2                ( 1UL << MCU_PLLP_OFFSET )  
#define MCU_PLLP_DIV3                ( 2UL << MCU_PLLP_OFFSET )  
#define MCU_PLLP_DIV4                ( 3UL << MCU_PLLP_OFFSET )  
#define MCU_PLLP_DIV5                ( 4UL << MCU_PLLP_OFFSET )  
#define MCU_PLLP_DIV6                ( 5UL << MCU_PLLP_OFFSET )  
#define MCU_PLLP_DIV7                ( 6UL << MCU_PLLP_OFFSET )  
#define MCU_PLLP_DIV8                ( 7UL << MCU_PLLP_OFFSET )  
#define MCU_PLLP_DIV9                ( 8UL << MCU_PLLP_OFFSET )  
#define MCU_PLLP_DIV10               ( 9UL << MCU_PLLP_OFFSET )  
#define MCU_PLLP_DIV11               ( 10UL << MCU_PLLP_OFFSET ) 
#define MCU_PLLP_DIV12               ( 11UL << MCU_PLLP_OFFSET ) 
#define MCU_PLLP_DIV13               ( 12UL << MCU_PLLP_OFFSET ) 
#define MCU_PLLP_DIV14               ( 13UL << MCU_PLLP_OFFSET ) 
#define MCU_PLLP_DIV15               ( 14UL << MCU_PLLP_OFFSET ) 
#define MCU_PLLP_DIV16               ( 15UL << MCU_PLLP_OFFSET ) 
#define MCU_PLLP_DIV17               ( 16UL << MCU_PLLP_OFFSET ) 
#define MCU_PLLP_DIV18               ( 17UL << MCU_PLLP_OFFSET ) 
#define MCU_PLLP_DIV19               ( 18UL << MCU_PLLP_OFFSET ) 
#define MCU_PLLP_DIV20               ( 19UL << MCU_PLLP_OFFSET ) 
#define MCU_PLLP_DIV21               ( 20UL << MCU_PLLP_OFFSET ) 
#define MCU_PLLP_DIV22               ( 21UL << MCU_PLLP_OFFSET ) 
#define MCU_PLLP_DIV23               ( 22UL << MCU_PLLP_OFFSET ) 
#define MCU_PLLP_DIV24               ( 23UL << MCU_PLLP_OFFSET ) 
#define MCU_PLLP_DIV25               ( 24UL << MCU_PLLP_OFFSET ) 
#define MCU_PLLP_DIV26               ( 25UL << MCU_PLLP_OFFSET ) 
#define MCU_PLLP_DIV27               ( 26UL << MCU_PLLP_OFFSET ) 
#define MCU_PLLP_DIV28               ( 27UL << MCU_PLLP_OFFSET ) 
#define MCU_PLLP_DIV29               ( 28UL << MCU_PLLP_OFFSET ) 
#define MCU_PLLP_DIV30               ( 29UL << MCU_PLLP_OFFSET ) 
#define MCU_PLLP_DIV31               ( 30UL << MCU_PLLP_OFFSET ) 
#define MCU_PLLP_DIV32               ( 31UL << MCU_PLLP_OFFSET ) 

#define MCU_PLLQ_OFFSET              25u                        
#define MCU_PLLQ_MASK                0x0E000000u                
#define MCU_PLLQ_DIV2                ( 1UL << MCU_PLLQ_OFFSET ) 
#define MCU_PLLQ_DIV3                ( 2UL << MCU_PLLQ_OFFSET ) 
#define MCU_PLLQ_DIV4                ( 3UL << MCU_PLLQ_OFFSET ) 
#define MCU_PLLQ_DIV5                ( 4UL << MCU_PLLQ_OFFSET ) 
#define MCU_PLLQ_DIV6                ( 5UL << MCU_PLLQ_OFFSET ) 
#define MCU_PLLQ_DIV7                ( 6UL << MCU_PLLQ_OFFSET ) 
#define MCU_PLLQ_DIV8                ( 7UL << MCU_PLLQ_OFFSET ) 

#define MCU_PLLR_OFFSET              9u                         
#define MCU_PLLR_MASK                0xE0000000u                
#define MCU_PLLR_DIV2                ( 1UL << MCU_PLLR_OFFSET ) 
#define MCU_PLLR_DIV3                ( 2UL << MCU_PLLR_OFFSET ) 
#define MCU_PLLR_DIV4                ( 3UL << MCU_PLLR_OFFSET ) 
#define MCU_PLLR_DIV5                ( 4UL << MCU_PLLR_OFFSET ) 
#define MCU_PLLR_DIV6                ( 5UL << MCU_PLLR_OFFSET ) 
#define MCU_PLLR_DIV7                ( 6UL << MCU_PLLR_OFFSET ) 
#define MCU_PLLR_DIV8                ( 7UL << MCU_PLLR_OFFSET ) 

#define MCU_OSCILLATORTYPE_NONE      0u 
#define MCU_OSCILLATORTYPE_HSE       1u 
#define MCU_OSCILLATORTYPE_HSI       2u 
#define MCU_OSCILLATORTYPE_LSE       3u 
#define MCU_OSCILLATORTYPE_LSI       4u 
#define MCU_OSCILLATORTYPE_HSI48     5u 

#define MCU_HSE_OFF                  0u 
#define MCU_HSE_ON                   1u 
#define MCU_HSE_BYPASS               2u 

#define MCU_LSE_OFF                  0u 
#define MCU_LSE_ON                   1u 
#define MCU_LSE_BYPASS               2u 

#define MCU_HSI_OFF                  0u  
#define MCU_HSI_ON                   1u  
#define MCU_HSICALIBRATION_DEFAULT   64u 

#define MCU_LSI_OFF                  0u 
#define MCU_LSI_ON                   1u 

#define MCU_HSI48_OFF                0u 
#define MCU_HSI48_ON                 1u 

#define MCU_HSI_DIV_OFFSET           11u                           
#define MCU_HSI_DIV_MASK             0x3800u                       
#define MCU_HSI_DIV1                 ( 0UL << MCU_HSI_DIV_OFFSET ) 
#define MCU_HSI_DIV2                 ( 1UL << MCU_HSI_DIV_OFFSET ) 
#define MCU_HSI_DIV4                 ( 2UL << MCU_HSI_DIV_OFFSET ) 
#define MCU_HSI_DIV8                 ( 3UL << MCU_HSI_DIV_OFFSET ) 
#define MCU_HSI_DIV16                ( 4UL << MCU_HSI_DIV_OFFSET ) 
#define MCU_HSI_DIV32                ( 5UL << MCU_HSI_DIV_OFFSET ) 
#define MCU_HSI_DIV64                ( 6UL << MCU_HSI_DIV_OFFSET ) 
#define MCU_HSI_DIV128               ( 7UL << MCU_HSI_DIV_OFFSET ) 

#define MCU_HSICALIBRATION_OFFSET    8u      
#define MCU_HSICALIBRATION_MASK      0x7F00u 
#define MCU_HSICALIBRATION_MIN_VALUE 0u      
#define MCU_HSICALIBRATION_MAX_VALUE 127u    

#define MCU_SYSCLKSOURCE_MASK        0x07u                             
#define MCU_SYSCLKSOURCE_OFFSET      0u                                
#define MCU_SYSCLKSOURCE_HSI         ( 0u << MCU_SYSCLKSOURCE_OFFSET ) 
#define MCU_SYSCLKSOURCE_HSE         ( 1u << MCU_SYSCLKSOURCE_OFFSET ) 
#define MCU_SYSCLKSOURCE_PLLCLK      ( 2u << MCU_SYSCLKSOURCE_OFFSET ) 
#define MCU_SYSCLKSOURCE_LSI         ( 3u << MCU_SYSCLKSOURCE_OFFSET ) 
#define MCU_SYSCLKSOURCE_LSE         ( 4u << MCU_SYSCLKSOURCE_OFFSET ) 

#define MCU_CLOCKTYPE_SYSCLK         0u 
#define MCU_CLOCKTYPE_HCLK           1u 
#define MCU_CLOCKTYPE_PCLK1          2u 

#define MCU_AHB_DIV_OFFSET           8u                             
#define MCU_AHB_DIV_MASK             0xF00u                         
#define MCU_AHB_DIV1                 ( 7UL << MCU_AHB_DIV_OFFSET )  
#define MCU_AHB_DIV2                 ( 8UL << MCU_AHB_DIV_OFFSET )  
#define MCU_AHB_DIV4                 ( 9UL << MCU_AHB_DIV_OFFSET )  
#define MCU_AHB_DIV8                 ( 10UL << MCU_AHB_DIV_OFFSET ) 
#define MCU_AHB_DIV16                ( 11UL << MCU_AHB_DIV_OFFSET ) 
#define MCU_AHB_DIV64                ( 12UL << MCU_AHB_DIV_OFFSET ) 
#define MCU_AHB_DIV128               ( 13UL << MCU_AHB_DIV_OFFSET ) 
#define MCU_AHB_DIV256               ( 14UL << MCU_AHB_DIV_OFFSET ) 
#define MCU_AHB_DIV512               ( 15UL << MCU_AHB_DIV_OFFSET ) 

#define MCU_APB1_DIV_OFFSET          12u                            
#define MCU_APB1_DIV_MASK            0x7000u                        
#define MCU_APB1_DIV1                ( 3UL << MCU_APB1_DIV_OFFSET ) 
#define MCU_APB1_DIV2                ( 4UL << MCU_APB1_DIV_OFFSET ) 
#define MCU_APB1_DIV4                ( 5UL << MCU_APB1_DIV_OFFSET ) 
#define MCU_APB1_DIV8                ( 6UL << MCU_APB1_DIV_OFFSET ) 
#define MCU_APB1_DIV16               ( 7UL << MCU_APB1_DIV_OFFSET ) 

#define MCU_PLL_STATE_DISABLED       0u 
#define MCU_PLL_STATE_ENABLED        1u 

typedef enum _Mcu_PllStatusType
{
    MCU_PLL_LOCKED = 0x00,   
    MCU_PLL_UNLOCKED,        
    MCU_PLL_STATUS_UNDEFINED 
} Mcu_PllStatusType;

typedef uint32 Mcu_ClockType;

typedef enum _Mcu_ResetType
{
    MCU_POWER_ON_RESET = 0x00, 
    MCU_WATCHDOG_RESET,        
    MCU_SW_RESET,              
    MCU_RESET_UNDEFINED        
} Mcu_ResetType;

typedef uint32 Mcu_RawResetType;

typedef uint32 Mcu_ModeType;

typedef uint32 Mcu_RamSectionType;

typedef enum _Mcu_RamStateType
{
    MCU_RAMSTATE_INVALID = 0x00, 
    MCU_RAMSTATE_VALID,          
} Mcu_RamStateType;

typedef enum _Mcu_StatusType
{
    MCU_STATE_UNINIT = 0x00, 
    MCU_STATE_INIT,          
} Mcu_StatusType;

typedef struct _Mcu_PllConfigType
{
    uint32 PllSource; 
    uint32 PllState;  
    uint32 PllM;      
    uint32 PLLN;      
    uint32 PllP;      
    uint32 PllQ;      
    uint32 PllR;      
} Mcu_PllConfigType;

typedef struct _Mcu_OscConfigType
{
    uint32 OscillatorType;      
    uint32 HSEState;            
    uint32 LSEState;            
    uint32 HSIState;            
    uint32 HSIDivider;          
    uint32 HSICalibrationValue; 
    uint32 LSIState;            
    uint32 HSI48State;          
    Mcu_PllConfigType PLL;      
} Mcu_OscConfigType;

typedef struct _Mcu_SysClkConfigType
{
    uint32 SysClockSource;   
    uint32 AHBClockDivider;  
    uint32 APB1ClockDivider; 
} Mcu_SysClkConfigType;

typedef struct _Mcu_ClkConfigType
{
    Mcu_OscConfigType OscConfig;    
    Mcu_SysClkConfigType ClkConfig; 
} Mcu_ClkConfigType;

typedef struct _Mcu_ConfigType
{
    Mcu_ClockType ClockSetting;    
    Mcu_ModeType McuMode;          
    Mcu_RamSectionType RamSection; 
    Mcu_PllStatusType PllStatus;   
    Mcu_ClkConfigType ClockConfig; 
} Mcu_ConfigType;

typedef struct _Mcu_HwUnit
{
    Mcu_ConfigType *Config;     
    Mcu_StatusType HwUnitState; 
} Mcu_HwUnit;
 
#endif